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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1999 mos integrated circuit pd16700 256-output tft-lcd gate driver data sheet document no. s14085ej3v0ds00 (3rd edition) date published june 2001 ns cp (k) printed in japan the mark ? ? ? ? shows major revised points. description the pd16700 is a tft-lcd gate driver equipped with 256-output lines. it can output a high-gate scanning voltage in response to cmos level input because it provided with a level-shift circuit inside the ic circuit. it can also drive the xga/sxga panel. features ? cmos level input (3.3 v) ? 256 outputs ? high-output voltage (v dd2 -v ee2 = amplitude: 40 v max.) ? capable of all-on outputting (/ao) remark /xxx indicates active low si gnal. ordering information part number package pd16700n-xxx tcp (tab package) remark the tcp?s external shape is customized. to order the required shape, please contact an one of our sales representatives.
data sheet s14085ej3v0ds 2 pd16700 1. block diagram ls1 o 1 sr1 ls1 ls1 clk stvr stvl oe 3 o 2 sr2 o 3 sr3 o 255 sr255 o 256 sr256 256-bit shift register ls1 o 254 sr254 ls1 r,/l v ee2 ls1 oe 1 ls1 oe 2 ls2 ls2 ls2 ls2 ls2 ls1 /ao ls2 note note note note note note note note note note note note note note note ls1: shifts cmos level and internal level, ls2: shifts interval level and output level (v dd2 -v ee2 ).
data sheet s14085ej3v0ds 3 pd16700 2. pin configuration ( pd16700n-xxx : copper foil surface, face-up) o 1 v ee2 o 2 v ee1 o 3 v ss stvr r , /l clk co pp er oe 1 foil oe 2 surface oe 3 stvl /ao v dd1 v dd2 o 254 o 255 o 256 remark this figure does not specify the tcp package.
data sheet s14085ej3v0ds 4 pd16700 3. pin functions pin symbol pin name i/o description o 1 to o 256 driver o these pins output scan signals that drive the vertical direction (gate lines) of a tft-lcd. the output signals change in synchronization with the rising edge of shift clock (clk). the driver output amplitude is v dd2 - v ee2 . r,/l shift direction select i refers to the shift direction control. the shift directions of shift registers are as follows. r,/l = h (right shift) : stvr o 1 o 256 stvl r,/l = l (left shift) : stvl o 256 o 1 stvr stvr, stvl start pulse i/o these refer to the input pins of the internal shift register. the start pulse is read at the rising edge of clk, and scan signals are output from the driver output pins. the input level is a cmos (3.3 v) level. the start pulse is output at the falling edge of the 256th clock of clk, and is cleared at the falling edge of the 257th clock. the output level is v dd1 - v ss (logic level). the output level is a cmos level (3.3 v). clk shift clock i this pin inputs a shift clock to the internal shift register. the shift operation is performed in synchronization with the rising edge of this input. oe 1 to oe 3 output enable i when these pins go h, the driver output is fixed to v ee2 level. the shift registers are not cleared. these pins are not synchronous with clk. oe 1 : o 1 , o 4 , ... o 250 , o 253 , o 256 oe 1 : o 2 , o 5 , ... o 251 , o 254 oe 1 : o 3 , o 6 , ... o 252 , o 255 /ao all-on control i when this pin goes l, the driver output is fixed to v dd2 level. the shift register is not cleared. this pin has priority over oe 1 to oe 3 . this pin is not synchronous with clk. v dd1 logic power supply ? 3.3 v 0.3 v v dd2 driver positive power supply ? 15 to 25 v the driver output : h level v ss logic ground ? connect this pin to the ground of the system. v ee1 negative power supply for internal operation ? ?15 to ?5 v v ee2 driver negative power supply ? the driver output : l level (v ee2 -v ee1 < 6.0 v) cautions 1. to prevent latch up, turn on power to v dd1 , v ee1/2 , v dd2 , and logic input in this order. turn off power in the reverse order. these power up/down sequence must be observed also during transition period. 2. insert a capacitor of about 0.1 f between each power line, as shown below, to secure noise margin such as v ih and v il . v dd2 v dd1 0.1 f v ss v ee1/2 0.1 f 0.1 f ? ? ?
data sheet s14085ej3v0ds 5 pd16700 4. timing chart (r,/l = h, /ao = h) clk 1 oe 3 o 1 (o 256 ) o 2 (o 255 ) stvl (stvr) o 1 of next stage (o 256 of next stage) o 2 of next stage (o 255 of next stage) 23 255 256 257 258 oe 1 stvr (stvl) oe 2 o 3 (o 254 ) o 255 (o 2 ) o 256 (o 1 ) 259
data sheet s14085ej3v0ds 6 pd16700 5. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol rating unit logic supply voltage v dd1 ?0.5 to +7.0 v driver positive supply voltage v dd2 ?0.5 to +28 v power supply voltage v dd2 -v ee1 , v ee2 ?0.5 to +42 v internal operation negative supply voltage v ee1 ?16 to + 0.5 v driver negative supply voltage v ee2 v ee1 ? 0.3 to v ee1 + 7.0 v input voltage v i ?0.5 to v dd1 + 0.5 v operating ambient temperature t a ?20 to +75 c storage temperature t stg ?55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?20 to +75 c, v ss = 0 v) parameter symbol min. typ. max. unit logic supply voltage v dd1 3.0 3.3 3.6 v driver positive supply voltage v dd2 15 23 25 v internal operation negative supply voltage v ee1 ?15 ?10 ?5.0 v power supply voltage v dd2- v ee1 20 33 40 v v ee2- v ee1 06.0v clock frequency f clk 100 khz electrical characteristics (t a = ?20 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 23 v, v ee1 = v ee2 = ?10 v, v ss = 0 v) parameter symbol condition min. typ. max. unit high-level input voltage v ih clk, stvr (stvl), r,/l, 0.8 v dd1 v dd1 v low-level input voltage v il oe 1 -oe 3 v ss 0.2 v dd1 v high-level output voltage v oh stvr (stvl), i oh = ?40 av dd1 ? 0.4 v dd1 v low-level output voltage v ol stvr (stvl), i ol = +40 av ss v ss + 0.4 v lcd driver output on resistance r on v out = v ee2 + 1.0 v, or v dd2 ? 1.0 v 0.25 1.0 k ? input leak current i il v i = 0 v or 3.6 v 1.0 a i dd1 v dd1 , f clk = 50 khz, oe 1 = oe 2 = oe 3 = l, f stv = 60 hz, no load 500 1000 a i dd2 v dd2 , f clk = 50 khz, oe 1 = oe 2 = oe 3 = l, f stv = 60 hz, no load 50 100 a static current dissipation i ee v ee1 , f clk = 50 khz, oe 1 = oe 2 = oe 3 = l, f stv = 60 hz, no load ?1100 ?550 a ?
data sheet s14085ej3v0ds 7 pd16700 switching characteristics (t a = ?20 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 23 v, v ee1 = v ee2 = ?10 v, v ss = 0 v) parameter symbol condition min. typ. max. unit cascade output delay time t phl1 c l = 20 pf, 240 800 ns t plh1 clk stvl (stvr) 240 800 ns driver output delay time t phl2 c l = 300 pf, clk o n 240 800 ns t plh2 240 800 ns t phl3 c l = 300 pf, oe n o n 240 800 ns t plh3 240 800 ns output rise time t tlh c l = 300 pf 350 ns output fall time t thl 350 ns input capacitance c i t a = 25 c 6.0 15 pf timing requirements (t a = ?20 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 23 v, v ee1 = v ee2 = ?10 v, v ss = 0 v) parameter symbol condition min. typ. max. unit clock pulse high width pw clk(h) 500 ns clock pulse low width pw clk(l) 500 ns enable pulse width pw oe 1.0 s data setup time t setup stvr (stvl) clk 200 ns data hold time t hold clk stvr(stvl) 200 ns caution keep the time and fall time of the logic input to t r = t f = 20 ns (10 to 90% of the rated values). remark unless otherwise specified, the input level is defined to be v ih = 0.8 v dd1 , v il = 0.2 v dd1 . for details, refer to switching characteristic waveform . ? ? ? ? ? ? ?
data sheet s14085ej3v0ds 8 pd16700 switching characteristic waveform (r,/l= h) unless otherwise specified, the input level is defined to be v ih = 0.8 v dd1 , v il = 0.2 v dd1 . t s e t u p clk stvr t r 90% 10% t h o ld pw c lk (h ) t f 1 253 254 2 3 t p lh 2 o 1 t p h l2 o 2 o 255 o 256 t p l h 1 stvl t p h l1 oe 1 -oe 3 t p h l3 o 1 - o 256 t p lh 3 4 5 6 7 255 256 ? 90% 10% t t lh t t h l pw o e pw c l k (l) 90% 10% 50% 90% 10% 50% 50% 50% 50%
data sheet s14085ej3v0ds 9 pd16700 6. recommended mounting conditions the following conditions must be met for mounting conditions of the pd16700. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. pd16700n- xxx : tcp (tab pack age) mounting condition mounting method condition thermocompression soldering heating tool 300 to 350 c, heating for 2 to 3 seconds : pressure 100g (per solder) acf (adhesive conductive film) temporary bonding 70 to 100 c: pressure 3 to 8 kg/cm 2 : time 3 to 5 sec. real bonding 165 to 180 c: pressure 25 to 45 kg/cm 2 : time 30 to 40 sec. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite,ltd). caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time.
data sheet s14085ej3v0ds 10 pd16700 [memo]
data sheet s14085ej3v0ds 11 pd16700 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16700 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades to nec?s semiconductor devices (c11531e) m8e 00. 4 the information in this document is current as of june, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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